https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85538
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2018-04-26
CC| |jakub at gcc dot gnu.org,
| |vmakarov at gcc dot gnu.org
Ever confirmed|0 |1
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Seems RA goes wild for some reason. Doesn't reproduce with
-O2 -march=skylake-avx512 -mtune=generic, but does e.g. with
-O2 -march=skylake-avx512 -mtune=intel.
Only two insns are involved in the f8:
(insn 10 8 12 2 (set (reg:DI 95)
(unspec:DI [
(subreg:V64QI (reg/v:V8DI 93 [ x ]) 0)
(reg:V64QI 22 xmm1 [ y ])
(const_int 0 [0])
] UNSPEC_PCMP)) "include/avx512bwintrin.h":3058 1740
{avx512bw_cmpv64qi3}
(expr_list:REG_DEAD (reg/v:V8DI 93 [ x ])
(expr_list:REG_DEAD (reg:V64QI 22 xmm1 [ y ])
(nil))))
(insn 12 10 13 2 (set (reg:CC 17 flags)
(unspec:CC [
(reg:DI 95)
(reg:DI 95)
] UNSPEC_KORTEST)) "include/avx512bwintrin.h":128 1398 {kortestdi}
(expr_list:REG_DEAD (reg:DI 95)
(nil)))
and IRA seems to think MASK_EVEX_REGS is most beneficial for r95.
That is what actually is used for the first insn, which has Yk constraint and
thus requires k1-k7 regs, but the second insn has k constraint, allows k0-k7
regs and for some reason the k1 value is moved through stack into k0.
Vlad, could you please have a look?
