[Bug target/85616] New: ARM target using -O2 may cause unaligned access

[denis_second at hotmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85616

            Bug ID: 85616
           Summary: ARM target using -O2 may cause unaligned access
           Product: gcc
           Version: 6.3.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: denis_second at hotmail dot com
  Target Milestone: ---

Created attachment 44052
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=44052&action=edit
c file

The 32-bit arm target using "-O2" optimization option may combine single stores
into a multi store without respecting the alignment requirement of stm
instruction.
ARM reference:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15414.html

The following output was produced using gcc version 6.3.1

simple code to recreate the issue:

extern "C" bool bugTest(unsigned char *buf_start)
{
    register unsigned int item1 asm("r2") = *(unsigned int *) &buf_start[12];
    register unsigned int item2    asm("r3")= *(unsigned int *) &buf_start[16];
    *(unsigned int *) &buf_start[0] = item1;
    *(unsigned int *) &buf_start[4] = item2;

    return 1;
}

gcc -march=armv7-a -O2 -o stm.o stm.c

objdump stm.o

00000000 <bugTest>:
   0:   e590200c        ldr     r2, [r0, #12]
   4:   e5903010        ldr     r3, [r0, #16]
   8:   e880000c        stm     r0, {r2, r3} <-- causing unaligned access if
buf_start wasn't on a word boundary
   c:   e12fff1e        bx      lr


If I turn off peephole2 optimization I get the expected assembly

gcc -march=armv7-a -O2 -fno-peephole2 -o stm.o stm.c

00000000 <bugTest>:
   0:   e590200c        ldr     r2, [r0, #12]
   4:   e5903010        ldr     r3, [r0, #16]
   8:   e5802000        str     r2, [r0]
   c:   e5803004        str     r3, [r0, #4]
  10:   e12fff1e        bx      lr