[Bug target/85730] complex code for modifying lowest byte in a 4-byte vector

[glisse at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85730

Marc Glisse <glisse at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2018-05-10
          Component|tree-optimization           |target
     Ever confirmed|0                           |1

--- Comment #1 from Marc Glisse <glisse at gcc dot gnu.org> ---
At gimple, the difference is essentially
  BIT_FIELD_REF <v, 8, 0> = _6;
vs
  v_9 = BIT_INSERT_EXPR <v_8(D), _4, 0 (8 bits)>;

Before combine, that translates to modifying a register directly

(insn 6 3 7 2 (set (reg:SI 93 [ v ])
        (sign_extend:SI (subreg:QI (reg/v:SI 92 [ v ]) 0))) "v.c":6 155
{extendqisi2}
     (nil))
(insn 7 6 8 2 (parallel [ 
            (set (reg:SI 94) 
                (ashift:SI (reg:SI 93 [ v ])
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) "v.c":6 550 {*ashlsi3_1}
     (expr_list:REG_DEAD (reg:SI 93 [ v ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))
(insn 8 7 13 2 (set (strict_low_part (subreg:QI (reg/v:SI 92 [ v ]) 0))
        (subreg:QI (reg:SI 94) 0)) "v.c":6 101 {*movstrictqi_1}
     (expr_list:REG_DEAD (reg:SI 94)
        (nil)))

or modifying a copy of it

        (sign_extend:SI (subreg:QI (reg/v:SI 92 [ v ]) 0))) "v.c":12 155
{extendqisi2}
     (nil))
(insn 7 6 9 2 (parallel [
            (set (reg:SI 94)
                (ashift:SI (reg:SI 93 [ v ])
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) "v.c":12 550 {*ashlsi3_1}
     (expr_list:REG_DEAD (reg:SI 93 [ v ])
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))
(insn 9 7 10 2 (set (reg:SI 96 [ v ])
        (reg/v:SI 92 [ v ])) "v.c":12 86 {*movsi_internal}
     (expr_list:REG_DEAD (reg/v:SI 92 [ v ])
        (nil)))
(insn 10 9 15 2 (set (strict_low_part (subreg:QI (reg:SI 96 [ v ]) 0))
        (subreg:QI (reg:SI 94) 0)) "v.c":12 101 {*movstrictqi_1}
     (expr_list:REG_DEAD (reg:SI 94)
        (nil)))

and combine only manages to match in the first case

(insn 8 7 13 2 (parallel [
            (set (strict_low_part (subreg:QI (reg/v:SI 92 [ v ]) 0)) 
                (ashift:QI (subreg:QI (reg/v:SI 92 [ v ]) 0) 
                    (const_int 1 [0x1])))
            (clobber (reg:CC 17 flags))
        ]) "v.c":6 556 {*ashlqi3_1_slp}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))

Operations on partial registers are often not so fast, but in any case it seems
that we should generate the same code for both cases. Either target or
rtl-optimization.