https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85745

            Bug ID: 85745
           Summary: variable with asm register assignment allocated in
                    wrong reg
           Product: gcc
           Version: 8.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: bernd.edlinger at hotmail dot de
  Target Milestone: ---

Created attachment 44114
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=44114&action=edit
reduced test case

This prevents linux v4.7 and before to be built with gcc-8.1.0 on armv7
targets.

$ arm-linux-gnueabihf-gcc -v
Using built-in specs.
COLLECT_GCC=arm-linux-gnueabihf-gcc
COLLECT_LTO_WRAPPER=/home/ed/gnu/arm-linux-gnueabihf-linux64/libexec/gcc/arm-linux-gnueabihf/8.1.0/lto-wrapper
Target: arm-linux-gnueabihf
Configured with: ../gcc-8.1.0/configure
--prefix=/home/ed/gnu/arm-linux-gnueabihf-linux64 --target=arm-linux-gnueabihf
--enable-languages=all --with-arch=armv7-a --with-tune=cortex-a9
--with-fpu=vfpv3-d16 --with-float=hard
Thread model: posix
gcc version 8.1.0 (GCC) 

$ arm-linux-gnueabihf-gcc -save-temps -Os -c test.c
test.s: Assembler messages:
test.s:39: Error: .err encountered


in test.s we see, that __r2 is allocated in r3 but that is unexpected,
it should have been r2:
sys_oabi_sendmsg:
        @ args = 0, pretend = 0, frame = 0
        @ frame_needed = 0, uses_anonymous_args = 0
        cmp     r1, #0
        bxeq    lr
        uxth    r2, r2
        cmp     r2, #1
        cmpeq   r0, #0
        bxne    lr
        mov     r3, #0
        str     lr, [sp, #-4]!
        ldr     r3, [r3]
        mov     r0, r1
        sub     r1, r3, #1
        mov     r3, #110
        .syntax divided
@ 37 "000.c" 1
        .ifnc r0,r0; .ifnc r0r0,fpr11; .ifnc r0r0,r11fp; .ifnc r0r0,ipr12;
.ifnc r0r0,r12ip; .err; .endif; .endif; .endif; .endif; .endif
        .ifnc r3,r2; .ifnc r3r2,fpr11; .ifnc r3r2,r11fp; .ifnc r3r2,ipr12;
.ifnc r3r2,r12ip; .err; .endif; .endif; .endif; .endif; .endif
        .ifnc r1,r1; .ifnc r1r1,fpr11; .ifnc r1r1,r11fp; .ifnc r1r1,ipr12;
.ifnc r1r1,r12ip; .err; .endif; .endif; .endif; .endif; .endif
        bl      __put_user_4
@ 0 "" 2
        .arm
        .syntax unified
        ldr     pc, [sp], #4


The after v4.8 this macro was a bit simplified, and causes less register
pressure, but I think it works only by chance.

I am not sure if that is a wrong expectation or a compiler bug.
It would be fixed when __r2 is declared volatile for instance.

Reply via email to