https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89435
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2019-02-21
CC| |jakub at gcc dot gnu.org,
| |segher at gcc dot gnu.org
Ever confirmed|0 |1
--- Comment #1 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
So, before combine we have:
(insn 106 2 23 2 (set (reg:SI 170 [+4 ])
(const_int 0 [0])) "pr89435.c":8:7 179 {*arm_movsi_insn}
(nil))
...
(insn 27 26 28 2 (set (reg:SI 142)
(const_int 255 [0xff])) "pr89435.c":9:7 179 {*arm_movsi_insn}
(nil))
...
(insn 27 26 28 2 (set (reg:SI 142)
(const_int 255 [0xff])) "pr89435.c":9:7 179 {*arm_movsi_insn}
(nil))
(insn 28 27 36 2 (parallel [
(set (reg:CC 100 cc)
(compare:CC (reg:SI 142)
(reg:SI 170 [+4 ])))
(set (reg:SI 141)
(minus:SI (reg:SI 142)
(reg:SI 170 [+4 ])))
]) "pr89435.c":9:7 28 {subsi3_compare1}
(expr_list:REG_DEAD (reg:SI 170 [+4 ])
(expr_list:REG_DEAD (reg:SI 142)
(expr_list:REG_UNUSED (reg:CC 100 cc)
(nil)))))
...
(insn 42 99 43 4 (set (reg:QI 125 [ _18 ])
(subreg:QI (reg:SI 141) 0)) "pr89435.c":9:7 189 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:SI 141)
(nil)))
...
(insn 77 76 78 8 (set (reg:SI 164)
(and:SI (subreg:SI (reg:QI 125 [ _18 ]) 0)
(const_int 255 [0xff]))) "pr89435.c":11:9 82 {*arm_andsi3_insn}
(expr_list:REG_DEAD (reg:QI 125 [ _18 ])
(nil)))
(insn 78 77 79 8 (set (reg:SI 124 [ _15 ])
(plus:SI (reg:SI 164)
(reg:SI 162))) "pr89435.c":11:9 4 {*arm_addsi3}
(expr_list:REG_DEAD (reg:SI 164)
(expr_list:REG_DEAD (reg:SI 162)
(nil))))
That looks good and will set (reg:SI 164) to 255.
Combiner makes:
(insn 28 27 36 2 (set (reg:SI 141)
(const_int 255 [0xff])) "pr89435.c":9:7 179 {*arm_movsi_insn}
(nil))
...
(insn 42 36 43 2 (set (reg:QI 125 [ _18 ])
(subreg:QI (reg:SI 141) 0)) "pr89435.c":9:7 189 {*arm_movqi_insn}
(expr_list:REG_DEAD (reg:SI 141)
(nil)))
...
(insn 78 77 79 7 (set (reg:SI 124 [ _15 ])
(plus:SI (reg:SI 162)
(subreg:SI (reg:QI 125 [ _18 ]) 0))) "pr89435.c":11:9 4
{*arm_addsi3}
(expr_list:REG_DEAD (reg:QI 125 [ _18 ])
(expr_list:REG_DEAD (reg:SI 162)
(nil))))
and that looks already wrong to me, because it has optimized away the &= 255.
The paradoxical register in the insn 78 means the upper bits are undefined, but
we really use the upper bits later on (fully 32-bit comparison). Either it
should have propagated the constant down, or it can't assume anything about the
paradoxical subreg bits (if they must not be ignored), because the RA can stick
the different pseudos into different registers, rather than setting a single hw
register to 0xff and then having the upper bits always zero.
