https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91233
Bug ID: 91233
Summary: Cannot build glibc for mips*r6 since r270955
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: middle-end
Assignee: unassigned at gcc dot gnu.org
Reporter: dragan.mladjeno...@rt-rk.com
CC: ubizjak at gmail dot com
Target Milestone: ---
Target: mips
We cannot use lo and hi register in clobber list for inline syscalls [1] since
r270955 for r6 targets. They don't have hi and lo registers available (at least
w/o dsp extension for time being).
~ cat test.c
void test () { __asm__ __volatile__("":::"lo"); }
~ ./gcc/xgcc -Bgcc -v
Reading specs from gcc/specs
COLLECT_GCC=./gcc/xgcc
COLLECT_LTO_WRAPPER=gcc/lto-wrapper
Target: mipsisa64-elf
Configured with: ../src/gcc/configure --target=mipsisa64-elf
--enable-languages=c
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 10.0.0 20190710 (experimental) (GCC)
~ ./gcc/xgcc -Bgcc -mips64r6 -mexplicit-relocs test.c -S -o /dev/null
test.c: In function ‘test’:
test.c:1:16: error: the register ‘lo’ cannot be clobbered in ‘asm’ for the
current target
1 | void test () { __asm__ __volatile__("":::"lo"); }
| ^~~~~~~
This will also affect other projects that provide a similar form of syscall
wrappers via inline assembly.
Is a reasonable compromise here to error out only if architecturally
unavailable "calle-saved" registers are found in the clobber list?
This should cover this use case and still prevent the backend for erroneously
trying to spill/restore unavailable register if that was the intention of the
original patch.
[1]
https://github.com/bminor/glibc/blob/7628a1b05adb1e4c6857b87c6f8b71a1d0b1d72c/sysdeps/unix/sysv/linux/mips/mips32/sysdep.h#L351
