https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92841
--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> --- There is a scheduling pass in between the peephole2 which this patch uses and the final pass, so it is possible there was some other instruction in between before scheduling, thus the peephole2 didn't trigger, later sched2 changes the order and now you see it. If we don't want to split the pattern and thus risk scheduling moving it away significantly etc., that will simply always happen, what matters is that the patch handles the common cases. And no, we aren't going to do anything about the cases where the register is set after several instructions, the clearing of the register is a security feature and we simply don't want to extend the exposure of the security sensitive data in any register.
