https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93230
--- Comment #2 from Michael Meissner <meissner at gcc dot gnu.org> ---
There is this code in rs6000.md that thinks it is combining the conversion with
the load, but the insn is using the wrong types:
;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<mode>_load"
[(set (match_operand:<VS_scalar> 0 "register_operand" "=r")
(vec_select:<VS_scalar>
(match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
(clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
operands[2],
operands[3], <VS_scalar>mode);
}
[(set_attr "type" "load")
(set_attr "length" "8")])
In addition, the code should also handle sign extension, and loading up the
value into a vector register.
