[Bug target/92692] [9/10 Regression] Saving off the callee saved register between ldxr/stxr (caused by shrink wrapping improvements)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92692

--- Comment #15 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Wilco Dijkstra <wi...@gcc.gnu.org>:

https://gcc.gnu.org/g:e5e07b68187b9aa334519746c45b8cffc5eb7e5c

commit r10-6038-ge5e07b68187b9aa334519746c45b8cffc5eb7e5c
Author: Wilco Dijkstra <wdijk...@arm.com>
Date:   Fri Jan 17 13:17:21 2020 +0000

    [AArch64] Fix shrinkwrapping interactions with atomics (PR92692)

    The separate shrinkwrapping pass may insert stores in the middle
    of atomics loops which can cause issues on some implementations.
    Avoid this by delaying splitting atomics patterns until after
    prolog/epilog generation.

    gcc/
        PR target/92692
        * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
        Add assert to ensure prolog has been emitted.
        (aarch64_split_atomic_op): Likewise.
        * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
        Use epilogue_completed rather than reload_completed.
        (aarch64_atomic_exchange<mode>): Likewise.
        (aarch64_atomic_<atomic_optab><mode>): Likewise.
        (atomic_nand<mode>): Likewise.
        (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
        (atomic_fetch_nand<mode>): Likewise.
        (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
        (atomic_nand_fetch<mode>): Likewise.