https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97329
Bug ID: 97329 Summary: POWER9 default cache and line sizes appear to be wrong Product: gcc Version: 10.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: kip at thevertigo dot com Target Milestone: --- While investigating the memory hierarchy on my Romulus POWER9 (CPU revision 2.2) I discovered GCC's default L1 cache and line sizes on POWER9 are not correct. I think whoever specified the default cache size of 64KB may not have realized the L1 cache is banked, and not unified. On POWER9 that 64KB is split between separate instructions and data spaces. Only 32KB is actually available for data. GCC's documentation specifies that the l1-cache-size parameter is suppose to refer to data only, but not instructions. Further, the default l1-cache-line-size is wrong. It's currently set at 32 bytes. The correct value is actually four times that at 128 bytes. As things are right now, the resulting generated code may not be properly optimized because the optimizer plans around the wrong parameters. When this happens the generated program may have a higher than necessary cache miss rate. This could be a big deal since the CPU retrieving data from the L1 may only take one or two cycles, but a cache miss could mean several hundred while the block is transferred.