> > Original asm is: > > __attribute__ ((noinline)) > int fls64(__u64 x) > { > int bitpos = -1; > asm("bsrq %1,%q0" > : "+r" (bitpos) > : "rm" (x)); > return bitpos + 1; > } > > There seems to be bug in bsr{q} pattern. I can make GCC produce same > code with: > > __attribute__ ((noinline)) > int > my_fls64 (__u64 x) > { > asm volatile ("movl $-1, %eax"); > return (__builtin_clzll (x) ^ 63) + 1; > }
Aha, bsr is not doing anything if parameter is 0, so pattern is correct (just the instruction is undefined for 0 which makes sense). But with that pattern GCC can't synthetize the code sequence above :) Honza