[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

[kito at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

--- Comment #37 from Kito Cheng <kito at gcc dot gnu.org> ---
Maybe we could add a parameter to indicate the type of memory access,
plain_mem, zext_mem or sext_mem for pass_shorten_memrefs::get_si_mem_base_reg.

e.g.
      for (int i = 0; i < 2; i++)
        {   
          rtx mem = XEXP (pat, i); 
          rtx addr;
          mem_access_type_t type;
          if (get_si_mem_base_reg (mem, &addr, &type))
            {   
              HOST_WIDE_INT regno = REGNO (XEXP (addr, 0));
              /* Do not transform store zero as these cannot be compressed.  */
              if (i == 0)
                {   
                  if (XEXP (pat, 1) == CONST0_RTX (GET_MODE (XEXP (pat, 1))))
                    continue;
                }   
              if (m->get_or_insert (regno) > 3)
                {
                  addr
                    = targetm.legitimize_address (addr, addr, GET_MODE (mem));
                  switch (type)
                    {
                    case plain_mem:
                      XEXP (pat, i) = replace_equiv_address (mem, addr);
                      break;
                    case zext_mem:
                      ...
                      break;
                    case sext_mem:
                      ...
                      break;
                    }
                  df_insn_rescan (insn);
                }   
            }