https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97873
--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
The attached patch generates:
movl %edi, %eax
negl %eax
cmovs %edi, %eax
ret
The patch changes CC mode of NEG instruction to CCGOCmode, which is the same
mode as the mode of SUB instruction. IOW, sign bit becomes usable.
We have r1 = neg (r0). The NEG insn sets sign flag (SF) based on the *result*,
so when the SF is set, we are sure that r1 holds the negative and consequently
r0 holds the positive value. Now, when SF is set, CMOVE should select r0 (the
positive mirror image), otherwise it should select r1. This is just how CMOVS
works.
The patch also changes the mode iterator of <maxmin:code><mode> patterns to
SWI48 instead of SWI248. The purpose of maxmin expander is to prepare max/min
RTX for STV to eventually convert them to SSE MAX/MIN instructions, in order to
*avoid* CMOV insns with general registers. HImode will not be converted, so it
can be expanded by middle-end to a generic shift/xor/sub sequence as well.
