https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98981
Jim Wilson <wilson at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |wilson at gcc dot gnu.org
--- Comment #1 from Jim Wilson <wilson at gcc dot gnu.org> ---
The extra move instruction is a side effect of how the riscv64 toolchain
handles 32-bit arithmetic. We lie to the compiler and tell it that we have
instructions that produce 32-bit results. In fact, we only have instructions
that produce 64-bit sign-extended 32-bit results. The lie means that the RTL
has some insns with SImode output and some instructions with DImode outputs,
and sometimes we end up with nop moves to convert between the modes. In this
case, it is peephole2 after regalloc that notices a SImode add followed by a
sign-extend, and converts it to a sign-extending 32-bit add followed by a move,
but can't eliminate the move because we already did register allocation.
This same problem is also why we get the unnecessary sext after the label, as
peephole can't fix that.
This problem has been on my todo list for a few years, and I have ideas of how
to fix it, but I have no idea when I will have time to try to fix it. I did
document it for the RISC-V International Code Speed Optimization task group.
https://github.com/riscv/riscv-code-speed-optimization/blob/main/projects/gcc-optimizations.adoc
This one is the first one in the list.
