https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99718
--- Comment #4 from luoxhu at gcc dot gnu.org --- Thanks, Jakub. It tested pass on both m32/m64, is this a reasonable fix? @segher, will make it a patch if so. git diff diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 859af75..0a5cae2 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1920,6 +1920,12 @@ return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT); }) +;; Return true if m64 on p8v and above for vec_set with variable index. +(define_predicate "vec_set_index_operand" + (if_then_else (match_test "TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT") + (match_operand 0 "reg_or_cint_operand") + (match_operand 0 "const_int_operand"))) + ;; Return true if the operand is a valid memory operand with a D-form ;; address that could be merged with the load of a PC-relative external address ;; with the PCREL_OPT optimization. We don't check here whether or not the diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index e5191bd..3446b03 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -1227,7 +1227,7 @@ (define_expand "vec_set<mode>" [(match_operand:VEC_E 0 "vlogical_operand") (match_operand:<VEC_base> 1 "register_operand") - (match_operand 2 "reg_or_cint_operand")] + (match_operand 2 "vec_set_index_operand")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { rs6000_expand_vector_set (operands[0], operands[1], operands[2]);