https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100263

--- Comment #5 from Stefan Schulze Frielinghaus <stefansf at linux dot ibm.com> 
---
It looks like a mode mismatch:

(insn 201 200 378 3 (set (reg:DI 17 %f2 [196])
        (const_int 1 [0x1])) "t.c":23:36 1467 {*movdi_64}
     (expr_list:REG_EQUIV (const_int 1 [0x1])
        (nil)))
...
(insn 312 44 313 4 (set (reg:QI 5 %r5 [orig:74 c__lsm_flag.21 ] [74])
        (reg:QI 17 %f2 [orig:198 l_lsm_flag.27 ] [198])) "t.c":13:14 1480
{*movqi}
     (nil))
...
(insn 245 244 246 41 (set (reg:SI 5 %r5 [orig:169 c__lsm_flag.21+-3 ] [169])
        (zero_extend:SI (reg:QI 5 %r5 [orig:74 c__lsm_flag.21 ] [74]))) 1652
{*zero_extendqisi2_extimm}
     (nil))
(note 246 245 247 41 NOTE_INSN_DELETED)
(jump_insn 247 246 248 41 (parallel [                                           
            (set (pc)
                (if_then_else (eq (reg:SI 5 %r5 [orig:169 c__lsm_flag.21+-3 ]
[169])
                        (const_int 0 [0]))
                    (label_ref 251)
                    (pc)))
            (clobber (reg:CC 33 %cc))
        ]) 1458 {*cmp_and_br_signed_si}
     (expr_list:REG_DEAD (reg:SI 5 %r5 [orig:169 c__lsm_flag.21+-3 ] [169])
        (expr_list:REG_UNUSED (reg:CC 33 %cc)
            (int_list:REG_BR_PROB 357913950 (nil))))
 -> 251)
(note 248 247 249 42 [bb 42] NOTE_INSN_BASIC_BLOCK)
(insn 249 248 250 42 (set (reg/f:DI 1 %r1 [170])
        (symbol_ref:DI ("*.LANCHOR0") [flags 0x182])) 1467 {*movdi_64}
     (expr_list:REG_EQUIV (symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
        (nil)))
(insn 250 249 251 42 (set (mem/c:QI (plus:DI (reg/f:DI 1 %r1 [170])
                (const_int 135 [0x87])) [0 MEM[(char *)&c + 107B]+0 S1 A8])
        (reg:QI 18 %f4 [orig:73 D.2339 ] [73])) 1480 {*movqi}
     (expr_list:REG_DEAD (reg:QI 18 %f4 [orig:73 D.2339 ] [73])
        (expr_list:REG_DEAD (reg/f:DI 1 %r1 [170])
            (nil))))

Register f2 is written to in DI mode and read from in QI mode. The final
assembler for the read is `vlgvb %r5,%v2,0`. Inspecting v2 via GDB we have:

  v2_int64 = {0x1, 0x0}

which means r5 is zero afterwards and therefore the condition r5==0 is always
true so the store from insn 250 never happens.

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