https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80355
--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>: https://gcc.gnu.org/g:7665af0b1a964b1baae3a59b22fcc420369c63cf commit r12-2835-g7665af0b1a964b1baae3a59b22fcc420369c63cf Author: Jakub Jelinek <ja...@redhat.com> Date: Tue Aug 10 11:34:53 2021 +0200 i386: Improve single operand AVX512F permutations [PR80355] On the following testcase we emit vmovdqa32 .LC0(%rip), %zmm1 vpermd %zmm0, %zmm1, %zmm0 and vmovdqa64 .LC1(%rip), %zmm1 vpermq %zmm0, %zmm1, %zmm0 instead of vshufi32x4 $78, %zmm0, %zmm0, %zmm0 and vshufi64x2 $78, %zmm0, %zmm0, %zmm0 we can emit with the patch. We have patterns that match two argument permutations for vshuf[if]*, but for one argument it doesn't trigger. Either we can add two patterns for that, or we would need to add another routine to i386-expand.c that would transform under certain condition these cases to the two argument vshuf*, doing it in sse.md looked simpler. We don't need this for 32-byte vectors, we already emit single insn permutation that doesn't need memory op there. 2021-08-10 Jakub Jelinek <ja...@redhat.com> PR target/80355 * config/i386/sse.md (*avx512f_shuf_<shuffletype>64x2_1<mask_name>_1, *avx512f_shuf_<shuffletype>32x4_1<mask_name>_1): New define_insn patterns. * gcc.target/i386/avx512f-pr80355-1.c: New test.
