https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102211
--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
According to *movsi_internal and *movdi_64bit, SImode, and DImode can be placed
into FP_REGS, but in riscv_hard_regno_mode_ok, SImode/DImode is not allowed to
be allocated as FP_REGS, the mismatch here caues the ICE.
Simple hack as
modified gcc/config/riscv/riscv.c
@@ -4553,7 +4553,9 @@ riscv_hard_regno_mode_ok (unsigned int regno,
machine_mode mode)
return false;
if (GET_MODE_CLASS (mode) != MODE_FLOAT
- && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
+ && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
+ && mode != E_SImode
+ && mode != E_DImode)
return false;
/* Only use callee-saved registers if a potential callee is guaranteed
Solved the issue.
foo:
fmv.d.x fa5,a0
fmul.s fa0,fa0,fa5
