https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102239
Bug ID: 102239
Summary: powerpc suboptimal boolean test of contiguous bits
Product: gcc
Version: 11.2.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: npiggin at gmail dot com
Target Milestone: ---
Target: powerpc64le-linux-gnu
gcc version 11.2.1 20210815 (Debian 11.2.0-2)
Build flags -O2
--- test.c ---
void foo(long arg)
{
if (arg & ((1UL << 33) | (1UL << 34)))
asm volatile("# if");
else
asm volatile("# else");
}
---
generates:
foo:
rldicr 3,3,29,1
srdi. 3,3,29
beq 0,.L6
# if
blr
.L6:
# else
blr
This test of multiple contiguous bits could be tested with a single instruction
with rldicr. or rldicl.
Those instructions do tend to be more expensive than the Rc=0 form (C2 cracked
on POWER9, slower pipe class on POWER10), but I think they should be better
than the current 2-instruction sequence.
