https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102783
Bug ID: 102783
Summary: [powerpc] FPSCR manipulations cannot be relied upon
Product: gcc
Version: 4.9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: pc at us dot ibm.com
Target Milestone: ---
On all Power targets which support hardware floating-point, there are a few
manipulations of the Floating-Point Status and Control Register (FPSCR) that
have side-effects for subsequent floating-point computation. For example,
changing the floating-point rounding mode, or changing whether floating-point
exceptions are enabled.
There are many ways to effect those manipulations:
- The set of fenv(1) calls
- A handful of builtins:
__builtin_fpscr_set_rn
__builtin_mtfsf
__builtin_mtfsb{0,1}
- Inline asm using the appropriate instructions (mffsce, mffscdrn{i},
mffscrn{i}, mtfsf{i}, mtfsb{0,1})
The problem is that if any of the above methods are not effected in an
out-of-line function, there is no way at present to restrict instruction
scheduling such that nearby floating-point computations are prevented from
moving before or after the FPSCR changes. (Possibly resulting in computation
using a wrong rounding mode, or unexpected FP exceptions.)
With asm statements, one could add artificial read and write dependencies to
the input or output (if any) of the FPSCR manipulations and
previous/subsequent FP computations, but this is not always practicable.
(Current glibc is an example.)
