https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102811
--- Comment #13 from Uroš Bizjak <ubizjak at gmail dot com> --- (In reply to Hongtao.liu from comment #12) > > > > Just noticed that for some reason two VPXORs are emitted. One should be > > enough for both VPINSRW insns. > > With new alternative in your attached match(vpblenw one), RA could reuse > zero register, w/o that, xmm0/xmm1 need to be explictly clear for the upper > bits. > vpblendw $1, %xmm1, %xmm2, %xmm1 # 14 [c=4 l=6] *vec_setv8hf_0/8 True, but I'd expect some post-reload(?) pass to propagate zeros and remove redundant initializations.
