https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104790
--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Andre Simoes Dias Vieira <avie...@gcc.gnu.org>: https://gcc.gnu.org/g:796f5220c808bc37adbd1081476589ab1a5d7ac3 commit r12-7538-g796f5220c808bc37adbd1081476589ab1a5d7ac3 Author: Andre Vieira <andre.simoesdiasvie...@arm.com> Date: Tue Mar 8 17:46:40 2022 +0000 arm: MVE: Relax addressing modes for full loads and stores This patch relaxes the addressing modes for the mve full load and stores (by full loads and stores I mean non-widening or narrowing loads and stores resp). The code before was requiring a LO_REGNUM for these, where this is only a requirement if the load is widening or the store narrowing. gcc/ChangeLog: PR target/104790 * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO. * config/arm/arm.cc (mve_vector_mem_operand): Relax constraint on base register for non widening loads or narrowing stores.
