https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105930
--- Comment #22 from Jakub Jelinek <jakub at gcc dot gnu.org> --- (In reply to Linus Torvalds from comment #21) > Whee. > > Why does gcc have that constraint, btw? I tried to look at the clang code > generation once more, and I don't *think* clang has the same constraint, and > maybe that is why it does so much better? Registers in RTL have just a single register number and mode (ok, it has some extra info, but not a set of registers). When it is a pseudo register, that doesn't constrain anything, it is just (reg:DI 175). But when it is a hard register, it still has just a single register number, so there is no way to express through that non-consecutive set of registers, so (reg:DI 4) needs to be di:si pair etc. If the wider registers are narrowed before register allocation, it is just a pair like (reg:SI 123) (reg:SI 256) and it can be allowed anywhere. If we wanted RA to allocate non-consecutive registers, we'd need to represent that differently (say as concatenation of SImode registers), but then it wouldn't be accepted by constraints and predicates of most of the define_insn_and_split patterns.
