https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106240
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2022-07-11
Ever confirmed|0 |1
Component|tree-optimization |target
CC| |mfortune at gmail dot com
Status|UNCONFIRMED |NEW
--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
So we're going
t.c:9:17: note: using normal nonmask vectors for _11 = _1 == _3;
t.c:9:17: note: can narrow to unsigned:5 without loss of precision: i_9 =
i_12 + 1;
t.c:9:17: note: vect_recog_bool_pattern: detected: iftmp.0_5 = _11 ? _1 : _2;
t.c:9:17: note: bool pattern recognized: patt_10 = _11 != 0 ? _1 : _2;
..
t.c:9:17: note: ==> examining statement: _11 = _1 == _3;
t.c:10:36: missed: not vectorized: relevant stmt not supported: _11 = _1 ==
_3;
t.c:9:17: missed: bad operation or unsupported loop bound.
> grep 'vcond\|vec_cmp' *.md
mips-msa.md:;; Same as MSA. Used by vcond to iterate two modes.
mips-msa.md:(define_expand "vcondu<MSA:mode><IMSA:mode>"
mips-msa.md:(define_expand "vcond<MSA:mode><MSA_2:mode>"
mips-msa.md:(define_expand "vec_cmp<MSA:mode><mode_i>"
mips-msa.md: mips_expand_vec_cmp_expr (operands);
mips-msa.md:(define_expand "vec_cmpu<IMSA:mode><mode_i>"
mips-msa.md: mips_expand_vec_cmp_expr (operands);
mips-ps-3d.md:(define_expand "vcondv2sfv2sf"
mips-ps-3d.md: mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
mips-ps-3d.md: mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
mips-ps-3d.md: mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
so we have limited support for vec_cmp and no support for vcond_mask.
Generally I'd blame it on the target to not provide optabs that map to the
actual ISA. Before the rev. we produced
$L2:
ldc1 $f1,0($4)
ldc1 $f0,0($2)
addiu $3,$3,8
add.ps $f2,$f1,$f3
addiu $2,$2,8
addiu $4,$4,8
c.eq.ps $fcc0,$f0,$f2
movf.ps $f0,$f1,$fcc0
.set noreorder
.set nomacro
bne $2,$5,$L2
I think
c.eq.ps $fcc0,$f0,$f2
movf.ps $f0,$f1,$fcc0
corresponds to
_34 = vect__1.8_28 == vect__3.12_33;
vect_iftmp.13_35 = VEC_COND_EXPR <_34, vect__1.8_28, vect__2.11_31>;
and ISEL makes
vect_iftmp.13_35 = .VCOND (vect__1.8_28, vect__3.12_33, vect__1.8_28,
vect__2.11_31, 113);
so while the target supports vcond the actual ISA has vec_cmp plus
vcond_mask instead which would map to the new GIMPLE IL constraints
nicely.
But indeed for targets where the ISA can do VCOND we mess this up
during pattern recognition, making "fixup" in vectorizable_*
difficult. It would possibly be best to emulate ISEL here and
pattern-recog iftmp.0_5 = _1 == _3 ? _1 : _2; instead (yeah,
embedded GENERIC cond - patterns still have those - they probably
should use "unchecked" .VCOND but with scalar ops ...).
I'm not sure how likely is a MIPS maintainer modernizing the vectorizer
patterns here? What's the "modern" parts? mips-msa.md or mips-ps-3d.md?
