https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
GGanesh <Ganesh.Gopalasubramanian at amd dot com> changed:
What |Removed |Added
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CC| |Ganesh.Gopalasubramanian@am
| |d.com
--- Comment #10 from GGanesh <Ganesh.Gopalasubramanian at amd dot com> ---
Apologies for late response!
We would update the AMD APM manuals in the next revision.
For all AMD architectures,
Processors that support AVX extend the atomicity for cacheable,
naturally-aligned single loads or stores from a quadword to a double quadword.
which means all 128b instructions, even the *MOVDQU instructions, are atomic if
they end up being naturally aligned.
Can we extend this patch to AMD processors as well. If not, I will plan to
submit the patch for stage-1!
