https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107988
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>: https://gcc.gnu.org/g:8c2451ba4601739654e2ea4907d6fa2a00d660aa commit r13-4699-g8c2451ba4601739654e2ea4907d6fa2a00d660aa Author: Tamar Christina <tamar.christ...@arm.com> Date: Wed Dec 14 13:54:28 2022 +0000 AArch64: div-by-255, ensure that arguments are registers. [PR107988] At -O0 (as opposed to e.g. volatile) we can get into the situation where the in0 and result RTL arguments passed to the division function are memory locations instead of registers. I think we could reject these early on by checking that the gimple values are GIMPLE registers, but I think it's better to handle it. As such I force them to registers and emit a move to the memory locations and leave it up to reload to handle. This fixes the ICE and still allows the optimization in these cases, which improves the code quality a lot. gcc/ChangeLog: PR target/107988 * config/aarch64/aarch64.cc (aarch64_vectorize_can_special_div_by_constant): Ensure input and output RTL are registers. gcc/testsuite/ChangeLog: PR target/107988 * gcc.target/aarch64/pr107988-1.c: New test.
