https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108583
--- Comment #23 from Tamar Christina <tnfchris at gcc dot gnu.org> --- (In reply to rguent...@suse.de from comment #22) > On Thu, 2 Feb 2023, tnfchris at gcc dot gnu.org wrote: > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108583 > > > > --- Comment #21 from Tamar Christina <tnfchris at gcc dot gnu.org> --- > > > > > > OK, so that's an ADD_HIGHPART_EXPR then? Though the highpart of an > > > add is only a single bit, isn't it? For scalar you'd use the > > > carry bit here and instructions like adc to consume it. Is addhn > > > to do such thing on vectors? > > > > > > > So I think this is the only new IFN we'd need. basically we only need one > > representing (a + b) >> n, for certain values of n we have a single > > instruction > > for others we reject it. > > But the ISA only implements n == width(a), so a true "highpart add". > So I'd add > > OPTAB_D (sadd_highpart_optab, "sadd$a3_highpart") > OPTAB_D (uadd_highpart_optab, "uadd$a3_highpart") > > only? That is it's QImode + QImode -> QImode with the carry bit in > the result (sign or zero-extended)? Sure that works I think, I'll do that then.
