[Bug target/108831] QImode binary ops with one zero-extracted argument can be optimized

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108831

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <u...@gcc.gnu.org>:

https://gcc.gnu.org/g:6245441e124846d0c3551f312d2feef598fe251c

commit r13-6118-g6245441e124846d0c3551f312d2feef598fe251c
Author: Uros Bizjak <ubiz...@gmail.com>
Date:   Fri Feb 17 17:00:12 2023 +0100

    ii386: Generate QImode binary ops with high-part input register [PR108831]

    Following testcase:

    --cut here--
    struct S
    {
      unsigned char pad1;
      unsigned char val;
      unsigned short pad2;
    };

    unsigned char
    test_add (unsigned char a, struct S b)
    {
      a += b.val;

      return a;
    }
    --cut here--

    should be compiled to something like:

            addb %dh, %al

    but is currently compiled to:

            movzbl  %dh, %edx
            addl    %edx, %eax

    The patch implements insn patterns that model QImode binary ops with
    high-part QImode input register.  These ops can not be encoded with
    REX prefix, so only Q registers and constant memory output operands
    are allowed on x86_64 targets.

    2023-02-17  Uroš Bizjak  <ubiz...@gmail.com>

    gcc/ChangeLog:

            PR target/108831
            * config/i386/predicates.md
            (nonimm_x64constmem_operand): New predicate.
            * config/i386/i386.md (*addqi_ext<mode>_0): New insn pattern.
            (*subqi_ext<mode>_0): Ditto.
            (*andqi_ext<mode>_0): Ditto.
            (*<any_or:code>qi_ext<mode>_0): Ditto.

    gcc/testsuite/ChangeLog:

            PR target/108831
            * gcc.target/i386/pr108831-1.c: New test.
            * gcc.target/i386/pr108831-2.c: Ditto.