https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109932
Kewen Lin <linkw at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Last reconfirmed| |2023-05-24 Status|UNCONFIRMED |ASSIGNED Ever confirmed|0 |1 CC| |linkw at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |linkw at gcc dot gnu.org Keywords| |ice-on-invalid-code --- Comment #1 from Kewen Lin <linkw at gcc dot gnu.org> --- Confirmed, thanks for reporting. Both bif __builtin_pack_vector_int128 and __builtin_unpack_vector_int128 are put in stanza power7 instead of vsx, so they miss to check vsx available or not. const vsq __builtin_pack_vector_int128 (unsigned long long, \ unsigned long long); PACK_V1TI packv1ti {} void __builtin_ppc_speculation_barrier (); SPECBARR speculation_barrier {} const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); UNPACK_V1TI unpackv1ti {} But the underlying insn patterns do need VSX support, see: (define_insn "pack<mode>" [(set (match_operand:FMOVE128_VSX 0 "register_operand" "=wa") (unspec:FMOVE128_VSX [(match_operand:DI 1 "register_operand" "wa") (match_operand:DI 2 "register_operand" "wa")] UNSPEC_PACK_128BIT))] "TARGET_VSX" // here "xxpermdi %x0,%x1,%x2,0" [(set_attr "type" "vecperm")]) (define_insn "unpack<mode>" [(set (match_operand:DI 0 "register_operand" "=wa,wa") (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa") (match_operand:QI 2 "const_0_to_1_operand" "O,i")] UNSPEC_UNPACK_128BIT))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" // here { if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0) return ASM_COMMENT_START " xxpermdi to same register"; operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3); return "xxpermdi %x0,%x1,%x1,%3"; } [(set_attr "type" "vecperm")]) ; Iterator for 128-bit VSX types for pack/unpack (define_mode_iterator FMOVE128_VSX [V1TI KF]) both vector_mem for V1TI and KF are VSX. So the fix would be to move these two bifs to be under stanza vsx.