[Bug c/110277] RISC-V: ICE when build RVV intrinsic float reduction with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110277

--- Comment #1 from Li Pan <pan2.li at intel dot com> ---
Meanwhile, the float reduction for FP16 is not well supported for both the
ZVE64 and ZVE32. We will try to fix them together with this bug.