https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110559
--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> --- This can be improved in parts by enabling register-pressure aware scheduling. The rest is due to the default issue rate of 1. Setting proper instruction latency will then obviously cause a bit more reordering but my tests haven't shown a lot of additional spilling. I'm going to set the scheduler options in a patch next week.
