https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111010
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |uros at gcc dot gnu.org,
| |vmakarov at gcc dot gnu.org
Keywords| |ice-on-valid-code,
| |missed-optimization, ra
--- Comment #6 from Richard Biener <rguenth at gcc dot gnu.org> ---
The culprit hardly is responsible - it's the RA failing, this can be fixed for
example by using -fschedule-insns -fsched-pressure.
I think this define-insn-and-split is a bit heavy-weight for i386 and a split
after reload given we allow arbitrary memory operands (in this case the
addressing modes are simple though)
(insn 109 283 243 9 (set (reg:DI 295)
(ior:DI (ashift:DI (zero_extend:DI (mem:SI (plus:SI (mult:SI (reg:SI
329 [orig:229 _118 ] [229])
(const_int 4 [0x4]))
(reg/f:SI 328 [orig:83 a.0_1 ] [83])) [3
MEM[(unsigned int *)_11]+0 S4 A32]))
(const_int 32 [0x20]))
(zero_extend:DI (mem:SI (plus:SI (mult:SI (reg:SI 294 [233])
(const_int 4 [0x4]))
(reg/f:SI 328 [orig:83 a.0_1 ] [83])) [3 MEM[(unsigned
int *)_15]+0 S4 A32])))) "t.c":15:7 680 {*concatsidi3_3}
(expr_list:REG_DEAD (reg/f:SI 328 [orig:83 a.0_1 ] [83])
(expr_list:REG_DEAD (reg:SI 329 [orig:229 _118 ] [229])
(expr_list:REG_DEAD (reg:SI 294 [233])
(nil)))))
this requires 5 GPRs (and it's not even the most complicated form of
addressing). I'm not sure if LRA is supposed to fix this up, spilling
the two MEMs will still result in 5 registers needed, and with
32bits that's somewhat difficult to have?
So IMHO this is a bug in the machine description.
The LRA dump isn't really enlightening, it seems to succeed for the above
insn:
0 Non input pseudo reload: reject++
1 Non pseudo reload: reject++
Cycle danger: overall += LRA_MAX_REJECT
alt=0,overall=608,losers=1,rld_nregs=1
0 Non pseudo reload: reject++
1 Non pseudo reload: reject++
alt=1,overall=2,losers=0,rld_nregs=0
Choosing alt 1 in insn 239: (0) m (1) re {*movsi_internal}
Creating newreg=292 from oldreg=97, assigning class GENERAL_REGS to
address r292
Creating newreg=293 from oldreg=157, assigning class INDEX_REGS to
address r293
Change to class INDEX_REGS for r292
Creating newreg=294 from oldreg=233, assigning class INDEX_REGS to
address r294
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
3 Non-pseudo reload: reject+=2
3 Non input pseudo reload: reject++
alt=0,overall=18,losers=2,rld_nregs=2
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
3 Non-pseudo reload: reject+=2
3 Non input pseudo reload: reject++
alt=1,overall=18,losers=2,rld_nregs=3
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
alt=2,overall=18,losers=2,rld_nregs=3
0 Non-pseudo reload: reject+=2
0 Non input pseudo reload: reject++
0 Early clobber: reject++
alt=3,overall=10,losers=1,rld_nregs=2
Choosing alt 3 in insn 109: (0) &r (1) m (3) m {*concatsidi3_3}
Creating newreg=295, assigning class GENERAL_REGS to r295
109:
r295:DI=zero_extend([r229:SI*0x4+r83:SI])<<0x20|zero_extend([r294:SI*0x4+r83:SI])
REG_DEAD r233:SI
REG_DEAD r229:SI
Inserting insn reload before:
240: r292:SI=r97:SI
241: r293:SI=r157:SI
242: r294:SI=r233:SI
Inserting insn reload after:
243: [r292:SI+r293:SI+0x8]=r295:DI
but then the ICE is very much later ...
****** Splitting a hard reg after assignment #2: ******
Hard reg 0 is preferable by r350 with profit 174
EMERGENCY DUMP:
