https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90323
Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://gcc.gnu.org/bugzill | |a/show_bug.cgi?id=64448 --- Comment #20 from Andrew Pinski <pinskia at gcc dot gnu.org> --- The aarch64 backend matches this: (insn 15 10 16 2 (set (reg/i:V4SI 32 v0) (xor:V4SI (and:V4SI (xor:V4SI (reg:V4SI 101) (reg:V4SI 102)) (reg:V4SI 103)) (reg:V4SI 101))) "/app/example.cpp":7:1 3103 {aarch64_simd_bslv4si_internal} for the `bit v0.16b, v1.16b, v2.16b` instruction. which was done r5-6601 (PR 64448) .