[Bug target/111634] RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111634

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #3 from Patrick O'Neill <patrick at rivosinc dot com> ---
Confirmed to be fixed on r14-4443-ga809a556dc0.

Built and ran testsuite on rv32/64gcv glibc/newlib with --enable-checking=rtl.
They all built successfully and no tests fail due to rtl checking!