https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111745
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by hongtao Liu <liuho...@gcc.gnu.org>: https://gcc.gnu.org/g:4efe9085d087a8d94261e4c38dd2ba840f3419ac commit r14-4549-g4efe9085d087a8d94261e4c38dd2ba840f3419ac Author: liuhongt <hongtao....@intel.com> Date: Tue Oct 10 11:32:09 2023 +0800 Refine predicate of operands[2] in divv4hf3 with register_operand. In the expander, it will emit below insn. rtx tmp = gen_rtx_VEC_CONCAT (V4SFmode, operands[2], force_reg (V2SFmode, CONST1_RTX (V2SFmode))); but *vec_concat<mode> only allow register_operand. gcc/ChangeLog: PR target/111745 * config/i386/mmx.md (divv4hf3): Refine predicate of operands[2] with register_operand. gcc/testsuite/ChangeLog: * gcc.target/i386/pr111745.c: New test.