https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112092
Bug ID: 112092
Summary: RISC-V: Wrong RVV code produced for vsetvl-11.c and
vsetvlmax-8.c
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Keywords: wrong-code
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: macro at orcam dot me.uk
Target Milestone: ---
Target: riscv*-*-*
There is incorrect code produced for
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c, where we have:
if (cond)
vl = __riscv_vsetvl_e32m1(avl);
else
vl = __riscv_vsetvl_e16mf2(avl);
however the relevant parts of the assembly produced are:
beq a5,zero,.L2
vsetvli zero,a6,e32,m1,tu,ma
.L3:
[...]
ret
.L2:
vsetvli zero,a6,e32,m1,tu,ma
j .L3
so both VSETVLI instructions are identical (and the whole conditional
redundant) while the former one is AFAICT supposed to be:
vsetvli zero,a6,e16,mf2,ta,ma
according to the intrinsic used. Additionally the pass condition of the
test case is too relaxed, making the test pass regardless.
RTL dumps indicate correct code generation up until the "vsetvl" pass,
where:
(insn 20 19 21 4 (set (reg/v:SI 16 a6 [orig:136 vl ] [136])
(unspec:SI [
(reg/v:SI 16 a6 [orig:147 avl ] [147])
(const_int 16 [0x10])
(const_int 7 [0x7])
(const_int 2 [0x2]) repeated x2
] UNSPEC_VSETVL))
".../gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c":12:10 1507
{vsetvlsi_no_side_effects}
(nil))
is replaced with:
(insn 58 19 21 4 (parallel [
(set (reg:SI 66 vl)
(unspec:SI [
(reg/v:SI 16 a6 [orig:147 avl ] [147])
(const_int 32 [0x20])
(const_int 0 [0])
] UNSPEC_VSETVL))
(set (reg:SI 67 vtype)
(unspec:SI [
(const_int 32 [0x20])
(const_int 0 [0]) repeated x2
(const_int 1 [0x1])
] UNSPEC_VSETVL))
]) ".../gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c":12:10
1505 {vsetvl_discard_resultsi}
(nil))
Similarly with vsetvlmax-8.c.
