https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110551
--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Roger Sayle <sa...@gcc.gnu.org>: https://gcc.gnu.org/g:89e5d902fc55ad375f149f25a84c516ad360a606 commit r14-4968-g89e5d902fc55ad375f149f25a84c516ad360a606 Author: Roger Sayle <ro...@nextmovesoftware.com> Date: Fri Oct 27 10:03:53 2023 +0100 PR target/110551: Fix reg allocation for widening multiplications on x86. This patch contains clean-ups of the widening multiplication patterns in i386.md, and provides variants of the existing highpart multiplication peephole2 transformations (that tidy up register allocation after reload), and thereby fixes PR target/110551, which is a superfluous move instruction. For the new test case, compiled on x86_64 with -O2. Before: mulx64: movabsq $-7046029254386353131, %rcx movq %rcx, %rax mulq %rdi xorq %rdx, %rax ret After: mulx64: movabsq $-7046029254386353131, %rax mulq %rdi xorq %rdx, %rax ret The clean-ups are (i) that operand 1 is consistently made register_operand and operand 2 becomes nonimmediate_operand, so that predicates match the constraints, (ii) the representation of the BMI2 mulx instruction is updated to use the new umul_highpart RTX, and (iii) because operands 0 and 1 have different modes in widening multiplications, "a" is a more appropriate constraint than "0" (which avoids spills/reloads containing SUBREGs). The new peephole2 transformations are based upon those at around line 9951 of i386.md, that begins with the comment ;; Highpart multiplication peephole2s to tweak register allocation. ;; mov imm,%rdx; mov %rdi,%rax; imulq %rdx -> mov imm,%rax; imulq %rdi 2023-10-27 Roger Sayle <ro...@nextmovesoftware.com> gcc/ChangeLog PR target/110551 * config/i386/i386.md (<u>mul<mode><dwi>3): Make operands 1 and 2 take "regiser_operand" and "nonimmediate_operand" respectively. (<u>mulqihi3): Likewise. (*bmi2_umul<mode><dwi>3_1): Operand 2 needs to be register_operand matching the %d constraint. Use umul_highpart RTX to represent the highpart multiplication. (*umul<mode><dwi>3_1): Operand 2 should use regiser_operand predicate, and "a" rather than "0" as operands 0 and 2 have different modes. (define_split): For mul to mulx conversion, use the new umul_highpart RTX representation. (*mul<mode><dwi>3_1): Operand 1 should be register_operand and the constraint %a as operands 0 and 1 have different modes. (*<u>mulqihi3_1): Operand 1 should be register_operand matching the constraint %0. (define_peephole2): Providing widening multiplication variants of the peephole2s that tweak highpart multiplication register allocation. gcc/testsuite/ChangeLog PR target/110551 * gcc.target/i386/pr110551.c: New test case.
