[Bug rtl-optimization/112278] New: lra: ICE in partial_subreg_p for mixture of AdvSIMD & SVE register asms

[rsandifo at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112278

            Bug ID: 112278
           Summary: lra: ICE in partial_subreg_p for mixture of AdvSIMD &
                    SVE register asms
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rsandifo at gcc dot gnu.org
  Target Milestone: ---

The following test, compiled with -march=armv8.2-a+sve, ICEs in
partial_subreg_p, called from new_insn_reg:

#include <arm_neon.h>
#include <arm_sve.h>

void
f (void)
{
  {
    register svint8_t v0 asm ("z0");
    asm volatile ("" : "=w" (v0));
  }
  {
    register int8x8x4_t v0 asm ("v0");
    asm volatile ("" : "=w" (v0));
  }
}

GCC 10 behaves similarly, so I don't think this is a regression.