[Bug target/112295] New: RISC-V: Short forward branch pessimisation for ALU operations

[macro at orcam dot me.uk via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112295

            Bug ID: 112295
           Summary: RISC-V: Short forward branch pessimisation for ALU
                    operations
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: enhancement
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: macro at orcam dot me.uk
  Target Milestone: ---
            Target: riscv*-*-*

We have a pessimisation in the RISC-V backend for TARGET_SFB_ALU.
This code:

int
addsifeq (double w, double x, int y, int z)
{
  return w == x ? y + z : y;
}

built with:

$ gcc -mtune=sifive-7-series -O1 addsifeq.c

compiles to this:

        feq.d   a4,fa0,fa1
        addw    a5,a0,a1
        bne     a4,zero,1f      # movcc
        mv      a5,a0
1:
        mv      a0,a5
        ret

however by avoiding the SFB optimisation, e.g. with:

$ gcc -mtune=sifive-5-series -O1 addsifeq.c

we get clearly superior code, which actually still benefits from SFB:

        feq.d   a5,fa0,fa1
        beq     a5,zero,.L2
        addw    a0,a0,a1
.L2:
        ret

This can be fixed by providing `addMcc' patterns for TARGET_SFB_ALU,
but how about other ALU operations?

Filing as a PR as I may or may not have time to work on this, so let's
have it written down.