https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109154
--- Comment #79 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>: https://gcc.gnu.org/g:ffd40d3b233d63c925cceb0dcd5a4fc8925e2993 commit r14-5288-gffd40d3b233d63c925cceb0dcd5a4fc8925e2993 Author: Tamar Christina <tamar.christ...@arm.com> Date: Thu Nov 9 14:18:48 2023 +0000 AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154] SVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has and so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR by immediate and would require a reload then use an unpredicated SVE ORR instead. This has both speed and size improvements. gcc/ChangeLog: PR tree-optimization/109154 * config/aarch64/aarch64.md (<optab><mode>3): Add SVE split case. * config/aarch64/aarch64-simd.md (ior<mode>3<vczle><vczbe>): Likewise. * config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New. gcc/testsuite/ChangeLog: PR tree-optimization/109154 * gcc.target/aarch64/sve/fneg-abs_1.c: Updated. * gcc.target/aarch64/sve/fneg-abs_2.c: Updated. * gcc.target/aarch64/sve/fneg-abs_4.c: Updated.
