https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112758
--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Oh, and the reason why given the above
(and:DI (subreg:DI (mem/c:SI (lo_sum:DI (reg/f:DI 144)
(symbol_ref:DI ("globalVar") [flags 0x86] <var_decl
0x7fffea1f9b40 globalVar>)) [1 globalVar+0 S4 A32]) 0)
(const_int -280375465082881 [0xffff00ffffffffff]))
is optimized into the zero extension is the following in combine.cc:
/* If the one operand is a paradoxical subreg of a register or memory and
the constant (limited to the smaller mode) has only zero bits where
the sub expression has known zero bits, this can be expressed as
a zero_extend. */
else if (GET_CODE (XEXP (x, 0)) == SUBREG)
{
rtx sub;
sub = XEXP (XEXP (x, 0), 0);
machine_mode sub_mode = GET_MODE (sub);
int sub_width;
if ((REG_P (sub) || MEM_P (sub))
&& GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
&& sub_width < mode_width)
{
unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
unsigned HOST_WIDE_INT mask;
/* original AND constant with all the known zero bits set */
mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
if ((mask & mode_mask) == mode_mask)
{
new_rtx = make_compound_operation (sub, next_code);
new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
true, false, in_code == COMPARE);
}
}
}
clearly, if the sign_bit_copies stuff is right for wordmode paradoxical SUBREGs
of smaller MEMs with load_extend_op (MEM_mode) == SIGN_EXTEND, then this
optimization
needs to punt if those conditions are met and sub is a MEM.
Will defer this to people actually using WORD_REGISTER_OPERATIONS arches,
fortunately
none of the ones I'm involved with on a daily basis is.
