https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112853
--- Comment #9 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Robin Dapp <rd...@gcc.gnu.org>: https://gcc.gnu.org/g:d9dd06ad51b7479f09acb88adf404664a1e18b2a commit r14-6404-gd9dd06ad51b7479f09acb88adf404664a1e18b2a Author: Robin Dapp <rd...@ventanamicro.com> Date: Fri Dec 8 12:50:01 2023 +0100 RISC-V: Recognize stepped series in expand_vec_perm_const. We currently try to recognize various forms of stepped (const_vector) sequence variants in expand_const_vector. Because of complications with canonicalization and encoding it is easier to identify such patterns in expand_vec_perm_const_1 already where perm.series_p () is available. This patch introduces shuffle_series as new permutation pattern and tries to recognize series like [base0 base1 base1 + step ...]. If such a series is found the series is expanded by expand_vec_series and a gather is emitted. On top the patch fixes the step recognition in expand_const_vector for stepped series where such a series would end up before. This fixes several execution failures when running code compiled for a scalable vector size of 128 on a target with vlen = 256 or higher. The problem was only noticed there because the encoding for a reversed [2 2]-element vector ("3 2 1 0") is { [1 2], [0 2], [1 4] }. Some testcases that failed were: vect-alias-check-18.c vect-alias-check-1.F90 pr64365.c On a 128-bit target, only the first two elements are used. The third element causing the complications only comes into effect at vlen = 256. With this patch the testsuite results are similar with vlen = 128, vlen = 256 as well as vlen = 512 (apart from the fixed-vlmax tests of course). gcc/ChangeLog: PR target/112853 * config/riscv/riscv-v.cc (expand_const_vector): Fix step calculation. (modulo_sel_indices): Also perform modulo for variable-length constants. (shuffle_series): Recognize series permutations. (expand_vec_perm_const_1): Add shuffle_series.
