https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113429
--- Comment #2 from Vineet Gupta <vineetg at gcc dot gnu.org> --- Here's my analysis as to whats going on in vsetvl pass. Reduced Test with annotated BBs. .globl __a_MOD_f .type __a_MOD_f, @function __a_MOD_f: ... ble s1,zero,.L49 slli a4,s1,3 li a3,32 addi a5,sp,48 bgeu a4,a3,.L67 <--- BB 14 li a3,16 bgeu a4,a3,.L68 <--- BB 16 .L36 li a3,8 bgeu a4,a3,.L69 <--- BB 18 .L37: vsetvli a5,s1,e8,mf4,ta,ma <--- (2) rtl insn 440 li a3,-2147483648 ... ... <--- BB 17 .L69: vsetvli a5,s1,e8,mf4,ta,ma vsetivli zero,8,e8,mf2,ta,ma vmv.v.i v1,0 vse8.v v1,0(a5) j .L37 <--- BB 15 (BUG manifests in BB 15) .L68: vsetvli a5,s1,e8,mf4,ta,ma <--- (1) rtl insn 472 (copy of insn 440): clobbers a5 (BUG) vsetivli zero,8,e8,mf2,ta,ma addi a3,a5,8 vmv.v.i v1,0 <--- insn 88 (imp) vse8.v v1,0(a5) vse8.v v1,0(a3) addi a4,a4,-16 li a3,8 bltu a4,a3,.L37 j .L69 The issue manifests in BB 15, but the issue is insn 440 making its way across BBs. The problem is introduced in Phase 2 (hack to disable phase 2 elides the issue). Phase 2: Lift up vsetvl info. Try lift up 0. ... ... ... Try lift up 2. Compute LCM earliest insert data: Expr[5]: VALID (insn 88, bb 14) Expr[6]: VALID (insn 88, bb 15) Expr[7]: VALID (insn 440, bb 16) earliest: Edge(BB 14 -> BB 16): n_bits = 15, set = {7 } Edge(BB 15 -> BB 16): n_bits = 15, set = {7 } Edge(BB 16 -> BB 18): n_bits = 15, set = {9 } Edge(BB 16 -> BB 17): n_bits = 15, set = {8 } Fused global info result: Change BB 14 from:VALID (insn 88, BB 14) to (higher probability):VALID (insn 440, BB 16) <--- likely issue ??? ... Try lift up 3. Compute LCM earliest insert data: Expr[5]: VALID (insn 440, bb 14) Expr[6]: VALID (insn 88, bb 15) Expr[7]: VALID (insn 440, bb 16) earliest: Edge(bb 14 -> bb 16): n_bits = 15, set = {7 } Edge(bb 14 -> bb 15): n_bits = 15, set = {6 } Edge(bb 15 -> bb 16): n_bits = 15, set = {7 } VSETVL infos after phase 2 BB 14: probability: 2.4% (guessed) Header vsetvl info:VALID (insn 440, BB 14) Footer vsetvl info:VALID (insn 440, BB 14) BB 15: probability: 1.2% (guessed) Header vsetvl info:VALID (insn 88, BB 15) <-- seem OK pertains to VMV insn Footer vsetvl info:VALID (insn 88, BB 15) insn 88 vsetvl info:VALID (insn 88, BB 15) BB 16: probability: 2.4% (guessed) Header vsetvl info:VALID (insn 440, BB 16) Footer vsetvl info:VALID (insn 440, BB 16) However... Phase 4: Insert, modify and remove vsetvl insns. Insert vsetvl info before insn 88: VALID (insn 88, BB 15) <--- OK VMV Demand fields: demand_sew_lmul demand_avl SEW=8, VLMUL=mf2, RATIO=16, MAX_SEW=64 TAIL_POLICY=agnostic, MASK_POLICY=agnostic AVL=(const_int 8 [0x8]) VL=(nil) scanning new insn with uid = 460. <--- OK: VSETVL of VMV Insert vsetvl insn before insn 88: (insn 460 94 88 15 (parallel [ (set (reg:SI 66 vl) (unspec:SI [ (const_int 8 [0x8]) repeated x2 (const_int 7 [0x7]) ] UNSPEC_VSETVL)) (set (reg:SI 67 vtype) (unspec:SI [ (const_int 8 [0x8]) (const_int 7 [0x7]) (const_int 1 [0x1]) repeated x2 ] UNSPEC_VSETVL)) ]) "cam4red.f90":96:18 discrim 2 -1 (nil)) Insert missed vsetvl info at edge (BB 14 -> BB 15): VALID (insn 440, BB 14) <-- BUG Demand fields: demand_ratio_only demand_avl SEW=8, VLMUL=mf4, RATIO=32, MAX_SEW=64 TAIL_POLICY=agnostic, MASK_POLICY=agnostic AVL=(reg:DI 9 s1 [orig:138 _37 ] [138]) VL=(reg:DI 15 a5 [orig:140 _42 ] [140]) Insert vsetvl insn 472: