https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114164
Bug ID: 114164
Summary: simdclone vectorization creates unsupported IL
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: rguenth at gcc dot gnu.org
Target Milestone: ---
For g++.dg/vect/pr68762-1.cc the simdclone vectorization with -mavx creates
mask__18.266_50 = vect__8.265_48 == { 0, 0, 0, 0 };
_52 = VEC_COND_EXPR <mask__18.266_50, { 1.0e+0, 1.0e+0, 1.0e+0, 1.0e+0 }, {
0.0, 0.0, 0.0, 0.0 }>;
_53 = _Z3bazd.simdclone.5 (_51, _52);
but this isn't supported with AVX since here are integer vectors involved
but AVX only has FP support.
This causes the later vector lowering pass to lower this to
- _35 = BIT_FIELD_REF <vect__8.265_48, 32, 0>;
- _40 = _35 == 0;
- _43 = _40 ? 1.0e+0 : 0.0;
- _59 = BIT_FIELD_REF <vect__8.265_48, 32, 32>;
- _62 = _59 == 0;
- _41 = _62 ? 1.0e+0 : 0.0;
- _60 = BIT_FIELD_REF <vect__8.265_48, 32, 64>;
- _64 = _60 == 0;
- _65 = _64 ? 1.0e+0 : 0.0;
- _30 = BIT_FIELD_REF <vect__8.265_48, 32, 96>;
- _31 = _30 == 0;
- _27 = _31 ? 1.0e+0 : 0.0;
- _52 = {_43, _41, _65, _27};
which is quite inefficient.
The vectorizer fails to verify the VEC_COND_EXPRs it creates are actually
supported by the target.
And the x86 target, for -mavx might actually support creating mask arguments
for in-branch OMP simd or if not it should probably not present them as
usable.
