https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114338

--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Why would that be better?  On a machine that does not lack registers, there's
more instruction-level parallelism in 
 (set (tmp) (-1))
 (set (tmp) (ashift (tmp) (count)))
 (and (x) (x) (tmp))

What's more, on Arm/AArch64 insns 2 and 3 can be merged into a single
instruction:

  (set (tmp) (-1))
  (set (x) (and (ashift (tmp) (count)) (x)))

which is definitely preferable to two register-controlled shifts.

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