https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114351
Bug ID: 114351 Summary: RISC-V: ICE when __attribute__((target("arch=+v")) and build with rv64gc -O3 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: pan2.li at intel dot com Target Milestone: --- Assume we have a sample code as below void __attribute__((target("arch=+v"))) add (int *a, int *b, int *out, unsigned count) { unsigned i; for (i = 0; i < count; i++) out[i] = a[i] + b[i]; } When build with -march=rv64gc -O3 there will be ICE as below: test.c: In function ‘add’: test.c:4:1: internal compiler error: Floating point exception 4 | { | ^ 0x1a5891b crash_signal /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/toplev.cc:319 0x7f0a7884251f ??? ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0 0x1f51ba4 riscv_hard_regno_nregs /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:8143 0x1967bb9 init_reg_modes_target() /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/reginfo.cc:471 0x13fc029 init_emit_regs() /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/emit-rtl.cc:6237 0x1a5b83d target_reinit() /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/toplev.cc:1936 0x35e374d save_target_globals() /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/target-globals.cc:92 0x35e381f save_target_globals_default_opts() /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/target-globals.cc:122 0x1f544cc riscv_save_restore_target_globals(tree_node*) /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9138 0x1f55c36 riscv_set_current_function /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9477 0x1505be7 invoke_set_current_function_hook /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/function.cc:4690 0x1505f60 allocate_struct_function(tree_node*, bool) /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/function.cc:4813 0x1044e33 store_parm_decls() /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-decl.cc:11084 0x10b8a54 c_parser_declaration_or_fndef /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:2975 0x10b62b7 c_parser_external_declaration /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:2046 0x10b5d2a c_parser_translation_unit /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:1900 0x110d5f4 c_parse_file() /home/pli/gcc/333/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/c/c-parser.cc:26889 0x11bd3f3 c_common_parse_file() Prepare a script for most vector arch combinations we will have: arch=+v Fail arch=+zve32x Fail arch=+zve32f Fail arch=+zve64x Fail arch=+zve64f Fail arch=+zve64d Fail arch=+zvl64b Pass arch=+zvl128b Pass arch=+zvl256b Pass arch=+zvl4096b Pass arch=+zve32x_zvl64b Fail arch=+zve32x_zvl128b Fail arch=+zve32x_zvl256b Fail arch=+zve32x_zvl4096b Fail arch=+zve32f_zvl64b Fail arch=+zve32f_zvl128b Fail arch=+zve32f_zvl256b Fail arch=+zve32f_zvl4096b Fail arch=+zve64x_zvl64b Fail arch=+zve64x_zvl128b Fail arch=+zve64x_zvl256b Fail arch=+zve64x_zvl4096b Fail arch=+zve64f_zvl64b Fail arch=+zve64f_zvl128b Fail arch=+zve64f_zvl256b Fail arch=+zve64f_zvl4096b Fail arch=+zve64d_zvl64b Fail arch=+zve64d_zvl128b Fail arch=+zve64d_zvl256b Fail arch=+zve64d_zvl4096b Fail The passed arch cannot vectorized but the -march=armv8-a -O3 with __attribute__((target("+sve2"))) can vectorize. I will try to fix this ICE soon.