https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790
--- Comment #7 from Matthias Schiffer <mschif...@universe-factory.net> --- (In reply to YunQiang Su from comment #6) > The attached patch cannot work now. > > It is not correct, and it happened work due to good luck that the same > register was allocated for these 2 instructions. I believe this is not the case. The gp init sequence is inserted very late, and no register allocation is involved - the use of registers $2 and $3 is hardcoded: https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/mips/mips.cc;h=b63d40a357b7c1f294e2c82062f0ef75fc307ba8;hb=HEAD#l12164
