[Bug rtl-optimization/115495] [15 Regression] ICE in smallest_mode_for_size, at stor-layout.cc:356 during combine on RISC-V rv64gcv_zvl256b at -O3

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115495

--- Comment #3 from Robin Dapp <rdapp at gcc dot gnu.org> ---
At first it looked very weird that we need 50 (or so) instructions to expand

;; MEM <vector(16) short int> [(short int *)&a] = vect_cst__21;

but then I realized that all the hoops we jump through are due to possible
misalignment.  Otherwise we could of course just emit a vector store.

So we don't ICE with -mno-vector-strict-align.

Going to look into the actual issue in the next days.