[Bug target/114139] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_macro_fusion_pair_p, at config/riscv/riscv.cc:8438 with -O2 -fpic -mexplicit-relocs -mcpu=sifive-p450

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114139

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <l...@gcc.gnu.org>:

https://gcc.gnu.org/g:fd536b8412d4dae42aa04739c06f99a915be6261

commit r15-1566-gfd536b8412d4dae42aa04739c06f99a915be6261
Author: Jeff Law <j...@ventanamicro.com>
Date:   Sun Jun 23 08:26:25 2024 -0600

    [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before
extracting INTVAL

    Run-of-the-mill checking issue.  We had something like (plus (reg) (reg))
and
    tried to extract INTVAL (XEXP (x, 1)) which of course blows up with
checking
    on.

    Fixed thusly.   Tested on riscv32-elf in my tester.  riscv64-elf is in
flight,
    but won't finish for a while due to other tasks in flight.

            PR target/114139
    gcc/
            * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Verify object
            is a CONST_INT before looking at INTVAL.

    gcc/testsuite/

            * gcc.target/riscv/pr114139.c: New test.