https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115612
Bug ID: 115612 Summary: powerpc: define_insn_and_splits calling gen_reg_rtx unconditionally Product: gcc Version: 15.0 Status: UNCONFIRMED Keywords: ice-on-valid-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org CC: dje at gcc dot gnu.org, linkw at gcc dot gnu.org, segher at gcc dot gnu.org Target Milestone: --- Target: powerpc*-*-* The late-combine pass is disabled by default for rs6000: /* One of the late-combine passes runs after register allocation and can match define_insn_and_splits that were previously used only before register allocation. Some of those define_insn_and_splits use gen_reg_rtx unconditionally. Disable late-combine by default until the define_insn_and_splits are fixed. */ if (!OPTION_SET_P (flag_late_combine_instructions)) flag_late_combine_instructions = 0; For example, compiling gcc.c-torture/compile/20021001-1.c with -Os -flate-combine-instructions results in: 0x9c34cb gen_reg_rtx(machine_mode) .././src/gcc/emit-rtl.cc:1177 0x1b248a7 gen_split_452(rtx_insn*, rtx_def**) .././src/gcc/config/rs6000/rs6000.md:13257 0x1c1c783 split_17 .././src/gcc/config/rs6000/rs6000.md:13254 0x1c1c783 split_insns(rtx_def*, rtx_insn*) .././src/gcc/config/rs6000/rs6000.md:12707 0x9c8847 try_split(rtx_def*, rtx_insn*, int) .././src/gcc/emit-rtl.cc:3941 0xe58963 split_insn .././src/gcc/recog.cc:3409 0xe5e3ef split_all_insns() .././src/gcc/recog.cc:3513 0xe5e5cb execute .././src/gcc/recog.cc:4482 due to: (define_insn_and_split "*<code><mode>_cc" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (fp_rev:GPR (match_operand:CCFP 1 "cc_reg_operand" "y") (const_int 0)))] "!flag_finite_math_only" "#" "&& 1" [(pc)] { rtx_code revcode = reverse_condition_maybe_unordered (<CODE>); rtx eq = gen_rtx_fmt_ee (revcode, <MODE>mode, operands[1], const0_rtx); rtx tmp = gen_reg_rtx (<MODE>mode); emit_move_insn (tmp, eq); emit_insn (gen_xor<mode>3 (operands[0], tmp, const1_rtx)); DONE; } [(set_attr "length" "12")]) The instruction can be matched before or after RA, but the split only works before RA. It looked from a quick scan like there were a few other instances of this (although the vast majority of define_insn_and_splits are written to work both before and after RA).